Some modern data interfaces may carry data signals in different modes at different times. For example, in digital camera interfaces, according to the Mobile Industry Processor Interface (MIPI) Display Interface (DSI)/Camera Serial Interface-2 (CSI-2) specification, Low Power (LP) mode single-ended signals and High Speed (HS) mode differential signals may be carried through the MIPI DSI/CSI-2 interface bus lines at different times. This may allow the interface to adjust trade off between power saving and high speed.
Normally to implement the protocol layer decoding, both LP mode signals and HS mode signals need to be converted from input lines to allow parallel and separate mode signal processing combined for use in protocol decoding, but the data interface carrying different mode signals at different times may require different bus line loading or termination. These requirements of loading and processing add complexity to the overall interface hardware.
Thus, there is a need for improved data interface compatible to standards like MIPI DSI/CSI-2 that can provide the correct bus line loading and signal processing while reducing overall hardware complexity.